One type of memory known in the art is double data rate synchronous dynamic random access memory (DDR SDRAM). In general, DDR SDRAM includes at least one array of memory cells. The memory cells in the array of memory cells are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Conductive word lines extend across the array of memory cells along the x-direction and conductive bit lines extend across the array of memory cells along the y-direction. A memory cell is located at each cross point of a word line and a bit line. Memory cells are accessed using a row address and a column address.
DDR SDRAM uses a main clock signal and data strobe (DQS) signals for executing commands within the memory. The clock signal is used as a reference for the timing of commands, such as read and write commands. DQS signals are used as references for latching input data into the memory and output data into an external device.
During a write operation, two bits, four bits, or another even number of bits are collected and processed in the memory at the same time to maximize the bandwidth of the memory. An input DQS signal and input data bits are supplied by an external device. The input data bits are collected by the memory on each transition of the input DQS signal. The data bits are typically center aligned with the rising and falling edges of the DQS signal for latching the data into the memory. At the first clock signal rising edge after the final DQS signal falling edge, the collection of data bits ends and internal processing begins.
As data communication frequencies increase, center aligning input data bits with the input DQS signal rising and falling edges inside the memory becomes increasingly difficult. Input buffers can have different output rise and fall times that lead to different propagation delays for low to high voltage level and high to low voltage level transitions. This mismatch in propagation delays results in mismatched setup and hold times or an increase in setup and hold times and slower data communication frequencies.